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Intel, TSMC and Samsung join forces on chip stacking technology

March 07, 2022，Source: https://asia.nikkei.com/

Intel, Taiwan Semiconductor Manufacturing and Samsung will work together to establish an industry standard for advanced chip-packaging technologies, the next key battleground in the race to build more powerful electronics devices.

The world’s three biggest chipmakers, along with several other tech companies, announced on Thursday that they will form a consortium for collaboration on next-generation chip packaging and stacking, the last steps in semiconductor manufacturing before chips are mounted onto print circuit boards and assembled into electronic devices.

The rare collaboration among the world’s chip players underscores how important the industry now considers these technologies. Top global chip developers and tech giants — from Advanced Micro Devices, Qualcomm and Arm, to Google Cloud, Meta and Microsoft — will also to participate in the consortium, as will ASE Technology Holding, the world’s biggest provider of chip packaging and testing services.

The consortium said it is open to more companies joining.

Previously, chip packaging was viewed as less crucial and technologically demanding than chip manufacturing itself. But the area has emerged as a major battleground for the world’s top chipmakers, namely Samsung, Intel and TSMC, as they seek to produce ever more powerful chips.

Semiconductor development until now has focused primarily on how to squeeze more transistors onto a chip — in general, more transistors translates to greater computing power. But as the space between transistors has shrunk to just a few nanometers, this approach has become more challenging, some to predict the end of Moore’s law, the postulate that the number of transistors on a chip doubles every two years. Thus, how to pack and stack tiny chips of different functions and features together in the most efficient way has become the key area most chipmakers are keen to develop.

The new consortium aims to establish a single chip packaging standard, dubbed Universal Chiplet Interconnect Express (UCIe), to create a new ecosystem and fuel collaboration in the packaging and stacking segments. Better ways of combining different types of chips — or so-called chiplets — in one package can create a more powerful chip system.

Google and AMD, both of which are participating in the consortium, were among the first adopters of TSMC’s most advanced 3D chip-stacking technologies.

Apple, which has not joined the consortium, was the first to use TSMC’s first chip packaging technologies developed in-house back in 2016 and has continued to use such technologies in its latest iPhone processors.

China’s tech champion, Huawei Technologies, which is not yet in the consortium either, is also pushing hard to develop in-house cutting-edge chip stacking and packaging, part of its moves to lessen the impacts of Washington’s crackdown on the company, Nikkei Asia reported earlier.

UCIe is set to provide a complete “die-to-die” interconnect standard that will make it easy for end users to mix and match chiplet components. This means they will be able to build customized systems-on-a-chip (SoC) using parts from different vendors. An individual chip is called a die before it is packaged.

英特尔、台积电和三星联手开发芯片封装堆叠技术

英特尔、台积电和三星将携手建立先进芯片封装技术的行业标准，这是在打造更强大电子器件和产品竞争中的关键战场。

全球三大芯片制造商与其它几家科技公司周四（3月3日）宣布，他们将组建一个联盟在下一代芯片封装和堆叠技术方面进行合作，该技术是将芯片安装到印刷电路板上并组装成电子产品之前的半导体制造技术中的最后一步。

全球芯片厂商之间罕见的合作凸显了业界现在对芯片封装和堆叠技术的重视程度。全球顶级芯片开发商和科技巨头--从超微半导体（AMD）、高通和 ARM，到谷歌云、Meta（Facebook）和微软--都将加入该联盟，全球最大的芯片封装和测试服务提供商 ASE Technology Holding（日月光集团）也将加入该联盟。

该联盟表示，它对更多公司的加入持开放态度。

以前芯片封装被认为不如芯片制造本身那么重要且技术要求低，但目前芯片封装领域已成为三星、英特尔和台积电等全球顶级芯片制造商寻求生产更强大芯片的主要战场。

迄今为止，半导体技术的发展主要集中在如何将更多的晶体管压缩到芯片上-- 一般来说更多的晶体管会转化为更强的算力。但随着晶体管的特征尺度缩小到只有几纳米，这种方法变得更具挑战性，并预示着摩尔定律的终结，其预测芯片上的晶体管数量每两年翻一番。因此，如何以最高效的方式将具有不同功能和特性的小芯片封装堆叠在一起，成为大多数芯片制造商亟待突破的关键领域。

新联盟旨在建立一个名为 Universal Chiplet Interconnect Express 【UCIe，即通用小芯片互联通道) 的单一芯片封装标准，以创建新的生态系统并促进封装和堆叠领域的合作。将不同类型的芯片（或所谓的小芯片）组合在一个封装中的更好方法可以创建更强大的芯片系统。

参与该联盟的谷歌和 AMD 是台积电最先进的 3D 芯片堆叠技术的首批采用者之一。

尚未加入该联盟的苹果公司早在 2016 年就率先使用了台积电内部开发的首批芯片封装技术，并继续在其最新的 iPhone 处理器中使用此类技术。

尚未加入该联盟的中国科技领头企业华为技术公司也在努力开发其内部的尖端芯片堆叠和封装技术，这是其减轻华盛顿对其制裁压力影响的举措的一部分，之前已有相关的报道。

通用小芯片互联快递UCIe 旨在提供完整的“die-to-die”互连标准，使最终用户可以轻松混合和匹配小芯片组件。这意味着他们将能够使用来自不同供应商的部件制造出定制的片上系统。

（翻译、校正：XPZ）