Personal Profile
Jiang xiaobo is an Associate Professor at South China University of Technology. His research interests include natural language processing (NLP), NLP-specific chip design, low-power integrated circuit design, error-control coding, and key technologies for emerging memory systems. He received his Ph.D. in Solid-State Electronics and Microelectronics from the Institute of Microelectronics, Chinese Academy of Sciences, in 2004. He then joined Samsung Electronics' Digital Media & Communications R&D Center in South Korea. From 1997 to 2001, he worked at the National Key Laboratory of Component Reliability Physics, China Electronics Technology Group Corporation No. 5 Research Institute (formerly under the Ministry of Information Industry). Between 1990 and 1997, he earned his Bachelor's and Master's degrees from the State Key Laboratory of Silicon Materials at Zhejiang University.
Education Background
2001.09-2004.06: Ph.D., Chinese Academy of Sciences
1994.08-1997.06: Master's Degree, Zhejiang University
1990.09-1994.07: Bachelor's Degree, Zhejiang University
Work Experience
2006.09-Present: South China University of Technology
2004.09-2006.08: Samsung Electronics, South Korea
1997.07-2001.08: China Electronics Standardization Institute (CESI)
Research Projects
Research Interests: Natural Language Processing (information extraction, natural language generation, financial-domain sentiment analysis); AI chip design; error-control code design.
Research Grants:
Design of Asynchronous Low-Power LDPC Decoders
Key Technologies for NAND Flash Memory Controller Chips
Development of LDPC Encoding and Decoding Techniques for Flash Memory
Application and Validation of AI Systems in Flash Memory
He has led or participated in more than ten research projects, published numerous academic papers, and holds multiple patents. One of his research outcomes has been successfully transferred for industrial application.
Courses Taught
Digital Systems Design, AI Chip Design
Flagship Achievements
Publications
1.Jiang xiaobo etc. “ Low power design of asynchronous datapath for LDPC decoder”. IEICE transactions on fundamentals of electronics,communications and computer sciences, vol.e96-a No.9 pp. 1857~1863, 2013-09-05.
2.Jiang xiaobo etc. “A novel comparator featured with input data characteristic.” International Journal of Electronics, 2015,4.
3.Jiang xiaobo etc. “Novel ECC Structure and evaluation letter for NAND Flash Memory”, IEEE SOCC 2015, 201509.
4.Jiang xiaobo etc.” Novel Reliability Evaluation Method for NAND Flash Memory”, IEEE TENCON 2015.
5.Jiang xiaobo and Nie Zhenghua, “Low-Complexity LDPC Decoding Algorithm for CMMB,” Acta Electronica Sinica, vol. 38, no. 7, pp. 1612-1615, 2010/7/15.
6.Jiang xiaobo and Ye Desheng, “A Novel Design Method for Low-Power Asynchronous Comparator,” Acta Electronica Sinica, vol. 40, no. 8, pp. 1650-1654, 2012/8/15.
7.Jiang xiaobo, “Design of Low-Power Asynchronous Datapath for LDPC Decoder,” Acta Electronica Sinica.
Granted Invention Patents
CN201110067464.0: Implementation Method of a Multi-Core Processor-Based Multi-Mode GNSS Software Receiver
CN201210265306.0: Configurable D Latch for Chaotic Computing
CN201210234683.8: LDPC Decoder and Decoding Method Based on Linear Programming
CN201110141433.5: TV Human-Computer Interaction Method Based on Handwriting Input and Fingertip Mouse
CN201110138040.9: Fingertip Mouse Interaction Method for TV Control
CN201110047021.5: Hardware Feature Box for Integral Image-Based Feature Search and Traversal
CN201110255821.6: Low-Power Asynchronous Comparator and Gating Circuit for LDPC Decoder
