时间:2014年11月7日(星期五)下午15:00
地点:大学城校区B5栋1楼会议室
报告摘要:
Among the candidate channel materials for the next generation electronic devices, semiconducting carbon nanotube (CNT) is unique in that it has no dangling bonds but has perfect Ohmic contacts to both the conduction and valence bands of the CNT. This is extremely important, since it provides the required chemical and mechanical stability of the devices, and renders both n-type and p-type FETs with performance close to ballistic limit available for CNT CMOS. CNT also has high carrier mobility and high saturation velocities, allowing high performance in long channel device where the transport is dominated by diffusive transport, and in short channel device where the device speed is determined by the saturation or Fermi velocity. In addition, a semiconducting CNT has a symmetric band structure near the Fermi level that gives identical effective mass for both electron and hole, leading to symmetric CMOS with potentially very low power consumption and compacted circuit layout. The atomic thickness of the CNT conduction channel is also extremely important in that it allows easier control of the channel current, making the scaling of the CNT technology possible down to 5nm transistor technology.
High performance CNT CMOS devices can be readily fabricated by a doping-free process using symmetric pairs of n-type (Sc or Y) and p-type (Pd) contacts, with demonstrated performance that compares favorably to the state of the art Si MOS FETs down to the very end of the roadmap. The feasibility of this doping free CMOS technology has been demonstrated by fabricating CMOS circuits, including a full adder and BUS circuits, on a SiO2/Si substrate, demonstrating perfect symmetric device characteristics for the n-type and p-type CNT FETs based on the same single walled CNT. This CNT based CMOS technology only requires the patterning of arrays of parallel semiconducting CNTs with moderately narrow diameter range, e.g. 1.5-2.5nm, instead of the more stringent chirality control on the CNT. This may lead to the integration of CNT based CMOS devices or entire carbon based circuit with increasing complexity and possibly find its way into logic and optoelectronic circuits. Precise control on the threshold voltage of the CNT FET is also possible by using gate metal with suitable work function. This threshold voltage control allows zero threshold voltage CMOS devices be fabricated, and highly efficient circuits be built with pass-transistor-logic (PTL) which is more efficient than CMOS and uses much less numbers of transistors for achieving the same logic function. The doping-free approach and ballistic transport of CNT also allow extremely low power supply be used in CNT circuits, the demonstrated 0.4V is significantly lower than the projected 0.56V for Si circuits around 2026, leading to the possibility of using CNT to extend the MOS FET toward the end of the road map.
附报告人简介:
彭练茅教授,北京大学电子学系主任、纳米器件物理与化学教育部重点实验室主任、国际晶体学联合会电子晶体学委员会主席、美国《应用物理杂志》副主编。1982年于北京大学无线电电子学系本科毕业,1988年于美国亚利桑那州立大学获博士学位。从2001年起先后3次任国家“973”计划项目和国家重大科学研究计划项目首席科学家,国家自然科学基金委员会创新研究群体负责人,中国晶体学会和中国电子显微镜学会副理事长。主要研究领域为纳电子及功能材料的合成与结构;基于纳米材料的高性能电子、光电子器件的制备,器件物理,碳基集成电路的实现和系统;纳米器件在化学、生物传感及能源方面的应用。迄今在国际学术刊物上发表SCI收录论文300余篇,第一作者专著1部(High-Energy Electron Diffraction and Microscopy, 牛津大学出版社)。1994年获首届国家杰出青年科学基金资助,1998年获求是科技基金会“杰出青年学者奖”。主持的“亚纳米碳管的稳定性研究”被选为2000年中国高等学校十大科技进展,入选2000年中国基础科学研究十大新闻;“定量电子显微学方法与氧化钛纳米结构研究”项目2010年获得国家自然科学奖二等奖;“实现碳纳米管的高效光伏倍增效应”项目入选2011年度“中国科学十大进展”;“高性能碳基纳米电子器件”项目获2013年度高等学校自然科学奖一等奖。2009年获“全国优秀博士学位论文指导教师”称号;2013年被评为北京大学首届“十佳导师”。