基本信息
职称：微电子学院副教授、博导、硕导
Title: Associate Professor, Doctoral & Graduate Supervisor, School of Microelectronics
联系方式：wenyang@scut.edu.cn
招生专业
个人简介
杨文，华南理工大学副教授，博士生导师，入选广东省高层次人才计划。博士毕业于美国中佛罗里达大学，长期深耕宽禁带半导体器件可靠性、功率半导体失效分析及数模混合集成电路可靠性领域。具有丰富的产业经验，曾就职于全球顶级半导体企业美国亚德诺半导体有限公司（ADI），主导数模混合集成电路的失效分析、工艺优化及良率提升，为多代工艺平台量产提供关键技术支撑。在IEEE EDL、APL、IEEE T-ED、IEEE IRPS等国际顶级期刊与会议发表论文20多篇，4次在IEEE IRPS、ISPSD等顶尖会议作口头报告，曾任IEEE EDS Orlando Section主席。目前主持及参与国家自然基金、广东省自然基金、广东省重点研发专项及国家重点实验开放课题等8项宽禁带功率半导体器件可靠性项目，与多家功率半导体器件头部机构建立有长期合作。
Dr. Wen Yang is an Associate Professor and Doctoral Supervisor at South China University of Technology, and has been recognized as a high-level talent in Guangdong Province. He earned his Ph.D. from the University of Central Florida, USA, and has extensive expertise in the reliability of wide-bandgap semiconductor devices, failure analysis of power semiconductors, and reliability of mixed-signal integrated circuits. With substantial industry experience, Dr. Yang previously worked at Analog Devices, Inc. (ADI), a leading global semiconductor company, where he led failure analysis, process optimization, and yield improvement for mixed-signal integrated circuits. His contributions provided critical technical support for the mass production of multiple process platforms. He has published over 20 papers in top-tier international journals and conferences, including IEEE EDL, APL, IEEE T-ED, and IEEE IRPS, and has delivered oral presentations four times at premier conferences such as IEEE IRPS and ISPSD. Dr. Yang also served as Chair of the IEEE EDS Orlando Section. Currently, he leads and participates in eight research projects focused on the reliability of wide-bandgap power semiconductor devices, funded by the National Natural Science Foundation of China, Guangdong Natural Science Foundation, Guangdong Key R&D Program, and Open Fund of State Key Laboratory. He maintains long-term collaborations with leading power semiconductor institutions.
教育经历
2017.08 – 2021.08, 中佛罗里达大学, 电子工程，博士
2015.09 – 2017.06, 电子科技大学，集成电路工程，硕士
2011.09 – 2015.06, 电子科技大学，数理基础科学，学士
工作经历
2022.08 至今, 华南理工大学，预聘副教授
2021.08 – 2022.07, Analog Devices, Inc.（ADI），研究员
研究方向
GaN/SiC等宽禁带功率半导体器件的失效机理、可靠性表征与寿命预测
新型GaN功率集成电路的设计、测试与可靠性提升
极端环境下高可靠功率半导体器件结构创新及工艺优化
基于先进封装技术的高可靠性功率集成电路设计
学术任职
IEEE Member, IEEE Electron Devices Society Member
曾任IEEE EDS Orlando Section主席
担任IEEE T-ED、IEEE JESTPE、IEEE T-DMR等多个国际期刊及会议审稿人
科研项目
1.国家自然科学基金-青年科学基金项目（C类），超低温环境下p-GaN HEMT功率器件栅极可靠性关键问题研究，30万元，在研，主持。
2.广东省自然科学基金-面上项目，鳍式氮化镓功率半导体器件栅极关键可靠性问题研究，10万元，在研，主持。
3.广东省自然科学基金区域联合基金-青年基金项目，极端应力下GaN FinFET功率半导体器件关键可靠性问题研究，10万元，在研，主持。
4.国家重点实验开放课题，车规级槽栅型碳化硅功率器件关键可靠性技术研究，10万元，在研，主持。
5.广东省南沙区重点研发专项，800V高压电动汽车平台车规级碳化硅功率器件关键可靠性技术，60万元，在研，合作方主持。
6.广州市应用基础研究专题-青年博士“启航”项目，GaN FinFET功率半导体器件极端应力下退化机理的研究，5万元，在研，主持。
7.广东省重点领域研发项目，汽车芯片安全可靠检测技术及应用，150万元，在研，参与。
8.企业合作项目，SiC功率半导体器件可靠性研究，25万元，在研，主持。
代表性科研成果
[1]C. Song, Wen Yang*, W. Wang, J. Liao, P. Wu, H. Jiang, S. Jiang, and B. Li. Trap Thawing-Induced Threshold Voltage Instability in p-GaN HEMTs at Cryogenic Temperatures During Pre-stress. IEEE Electron Device Letters, vol. 46, no. 8, pp. 1289-1292, 2025.
[2]Wen Yang, and Jiann-Shiun Yuan. Substrate bias enhanced trap effects on time-dependent dielectric breakdown of GaN MIS-HEMTs. IEEE Transactions on Electron Devices, vol. 68, no. 5, pp. 2233-2239, 2021.
[3]Wen Yang, and Jiann-Shiun Yuan. Experimental investigation of buffer traps physical mechanisms on the gate charge of GaN-on-Si devices under various substrate biases. Applied Physics Letters, vol. 116, no. 8, pp. 083501, 2020.
[4]C. Song, Wen Yang*, Huaxing Jiang, and Bin Li. 3D-simulation design of a high current capacity GaN tri-gate power device with integrated parasitic bipolar junction. Semiconductor Science and Technology, vol. 40, no. 1, pp. 015001, 2024.
[5]Wen Yang, Jiann-Shiun Yuan, Balakrishnan Krishnan, and Patrick Shea. Characterization of Deep and Shallow traps in GaN HEMT using multi-frequency C-V measurement and pulse-mode voltage stress. IEEE Transactions on Device and Materials Reliability, vol. 19, no. 2, pp. 350-357, 2019.
[6]Wen Yang, Nicholas Stoll, and Jiann-Shiun Yuan. ESD Stress Effect on Failure Mechanisms in GaN-on-Si Power Device. IEEE Transactions on Device and Materials Reliability, vol. 21, no. 4, pp. 479-485, 2021.
[7]Wen Yang, and Jiann-Shiun Yuan. Negative-Bias Temperature Instability of p-GaN Gate GaN-on-Si Power Devices. IEEE Transactions on Device and Materials Reliability, vol. 22, no. 2, pp. 217-222, 2022.
[8]Wen Yang, Jiann-Shiun Yuan, Balakrishnan Krishnan, and Patrick Shea. Low-side gan power device dynamic r on characteristics under different substrate biases. in 2019 IEEE International Reliability Physics Symposium (IRPS), pp. 1-7, 2019. (Oral)
[9]C. Song, Wen Yang*, et al., Bidirectional Threshold Voltage Shift After Positive Bias Temperature Instability of p-GaN HEMTs at Cryogenic Temperature, IEEE International Reliability Physics Symposium (IRPS), pp. 1-5, 2025,
[10]Wen Yang, Nicholas Stoll, and Jiann-Shiun Yuan. ESD robustness of GaN-on-Si power devices under substrate biases by means of TLP/VFTLP tests. in 2020 IEEE International Reliability Physics Symposium (IRPS), pp. 1-5, 2020.
[11]Wen Yang, Jiann-Shiun Yuan, Balakrishnan Krishnan, An-Jye Tzou, and Wen-Kuan Yeh. Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated Gan Half-bridge. n 2020 IEEE International Reliability Physics Symposium (IRPS), pp. 1-5, 2020.
[12]P. Wu, Wen Yang*, C. Song, H. Jiang and B. Li, A Novel Split-Gate GaN Reverse Conduction FinFET Device with Lower Dead-Time Power Losses, IEEE 11th Workshop on Wide Bandgap Power Devices & Applications (WiPDA), pp. 1-5, 2024.